SH7708 Datasheet, PDF (20/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 1.1 SH7708 Series Features
Item
Features
CPU
• Original Hitachi SuperH RISC engine architecture
• 32-bit internal data bus
• General-register machine
 Sixteen 32-bit general registers (eight 32-bit bank registers)
 Five 32-bit control registers
 Four 32-bit system registers
• RISC-type instruction set (upward compatibility with the SH-1 and SH-2
series)
 Instruction length: 16-bit fixed length for improved code efficiency
 Load-store architecture
 Delayed branch instructions
 C-oriented instruction set
• Instruction execution time: one instruction/cycle for basic instructions
• Logical address space: 4 Gbytes (448-Mbyte actual memory space)
• Space identifier ASID: 8 bits, 256 logical address spaces
• On-chip multiplier
• Five-stage pipeline
Operating modes, •
clock pulse
generator
•
Clock mode: selected from an on-chip oscillator module, a frequency-
doubling circuit, or a clock output by combining them by PLL synchronization
Processing states:
 Power-on reset state
 Manual reset state
 Exception processing state
 Program execution state
 Power-down state
 Bus-released state
• Power-down modes:
 Sleep mode
 Standby mode
 Hardware Standby mode(SH7708S, SH7708R only)
• On-chip clock pulse generator
• One watchdog timer channel
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