SH7708 Datasheet, PDF (369/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

13.2.7 Serial Status Register (SCSSR)
The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and
status flags that indicate the SCI operating status.
The CPU can always read and write to SCSSR, but cannot write 1 in the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
SCSSR is initialized to H'84 by a reset and in standby or module standby mode.
Bit: 7
6
5
Bit name: TDRE RDRF ORER
Initial value: 1
0
0
R/W: R/(W)* R/(W)* R/(W)*
Note: Only 0 can be written, to clear the flag.
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from SCTDR into SCTSR and new serial transmit data can be written in SCTDR.
Bit 7: TDRE
0
1
Description
SCTDR contains valid transmit data.
TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE, or data is written in SCTDR.
SCTDR does not contain valid transmit data.
(Initial value)
TDRE is set to 1 when the chip is reset or enters standby mode, the TE bit in the
serial control register (SCSCR) is cleared to 0, or SCTDR contents are loaded
into SCTSR, so new data can be written in SCTDR.
351