SH7708 Datasheet, PDF (194/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

3. In clock modes 3 and 4, the SH7708 Series cannot go to standby mode while PLL
circuit 1 is on. Always set PSTBY and PLLEN to 0 to stop PLL circuit 1 before going
to standby mode.
4. When PSTBY and PLLEN are both changed from 0 to 1 together, the WDT will
automatically start counting and the clock will switch when the WDT overflows. See
section 9.5, Changing the Frequency, for setting the WDT.
PSTBY = 1
and PLLEN = 0
PLL1
off
PSTBY = 0
and PLLEN = 0
PSTBY = 1
(STC)
PSTBY = 0
(STC)
PLL1
standby
PLLEN = 1
(IFC, PFC)
PLLEN = 0
(STC, IFC, PFC)
PSTBY = 0, PLLEN = 0
(STC, IFC, PFC)
PLL1
on
PSTBY = 1
and PLLEN = 1
Note: Bits in parentheses can be changed simultaneously.
Figure 9.3 State Transitions for the PLL Standby Function
9.7 Controlling Clock Output
The CKOEN bit in the FRQCR register can be used to switch between outputting a clock to the
CKIO pin or having the level fixed.
9.7.1 Clock Modes 0–2
The CKIO pin level cannot be fixed. Always set the CKOEN bit in FRQCR to 1 (clock output).
9.7.2 Clock Modes 3 and 4
The CKIO output changes as soon as the CKOEN bit is changed. When the WDT is started by
simultaneously changing the multiplication rate of PLL circuit 1 or switching PLL circuit 1 on or
off, the WDT starts running after the CKIO output is switched, and then the internal clock
changes.
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