SH7708 Datasheet, PDF (318/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.4.5 Note on DRAM Connection for Areas 2 and 3
When area 2 or area 3 is connected to DRAM in the SH7708 or SH7708S, if a DRAM access
request occurs immediately after a CAS-before-RAS refresh, the RAS precharge cycle value (tPC)
always assumes its initial value regardless of the value set in MCR. Thus, the interval from RAS
negation to the next RAS assertion in CAS-before-RAS refreshing is a two-cycle output interval
(see figure below).
If a request does not immediately follow a CAS-before-RAS refresh, the number of RAS
precharge cycles set by the MCR value are secured.
CKIO
RAS
RAS negation
in CAS-before-
RAS refreshing
Two cycles
RAS asserted by
next bus access
Restriction: If a DRAM access request occurs immediately after a CAS-before-RAS refresh, the
interval from RAS negation to the next RAS assertion is two cycles.
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