SH7708 Datasheet, PDF (150/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

7.2.11 Break Control Register (BRCR)
Bit: 15
14
13
12
11
10
9
8
Bit name: CMFA CMFB —
—
—
PCBA
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W
R
R
R
R/W
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name: DBEB PCBB —
—
SEQ
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W
R
R
R/W
R
R
R
The break control register (BRCR) is a 16-bit read/write register that controls user breaks.
BRCR:
1. Determines whether to use channels A and B as two independent channels or as sequential
conditions.
2. Selects whether to break before or after instruction execution during the instruction fetch cycle.
3. Determines whether to include the BDRB register in the channel B comparison conditions.
It also has a condition-match flag. A power-on or manual reset initializes BRCR to H'0000.
Bit 15—Condition Match Flag A (CMFA): Set to 1 when the break conditions set in channel A are
met. Not cleared to 0. To check a flag setting after it has been set, clear it by writing 0.
Bit 15: CMFA
0
1
Description
Channel A break conditions do not match.
Channel A break conditions match.
(Initial value)
Bit 14—Condition Match Flag B (CMFB): Set to 1 when the break conditions set in channel B are
met. Not cleared to 0. To check a flag setting after it has been set, clear it by writing 0.
Bit 14: CMFB
0
1
Description
Channel B break conditions do not match.
Channel B break conditions match.
(Initial value)
Bits 13 to 11—Reserved: These bits always read 0. The write value should always be 0.
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