SH7708 Datasheet, PDF (160/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 8.1 Power-Down Modes
State
Mode
Transition
Conditions
CPU
On-Chip
Reg- On-Chip Peripheral
External Canceling
CPG CPU ister Memory Modules Pins Memory Procedure
Sleep Execute SLEEP Runs Halts Held Held
Run
mode instruction with
(Reg-
STBY bit cleared
ister
to 0 in STBCR
held)
Held Refresh 1. Interrupt
2. Reset
Standby
mode
Execute SLEEP Halts
instruction with
STBY bit set to 1
in STBCR
Halts Held
(Reg-
ister
held)
Held
Halts*¹
Held Self- 1. Interrupt
refresh 2. Reset
Hardware Drive CA pin
standby low
mode
Halts
Halts
(Reg-
ister
held)
Held
Held
Halts*³
Held Self- Power-on
refresh reset
Module Set MSTP bit of Runs Runs Held Held
standby STBCR to 1
Specified *²
module
halts
Refresh
1. Clear
MSTP
bit to 0
2. Reset
Notes: 1. The RTC still runs if the START bit in RCR2 is set to 1 (see section 12, Realtime Clock
(RTC)). TMU still runs when output of the RTC is used as input to its counter (see
section 11, Timer (TMU)).
2. Depends on the on-chip supporting module.
TMU external pin: Held
SCI external pin: Reset
3. The RTC still runs if the START bit in RCR2 is set to 1 (see section 12, Realtime Clock
(RTC)). The TMU does not run.
8.1.2 Register Configuration
Table 8.2 shows the configuration of the control register for the power-down modes.
Table 8.2 Register Configuration
Name
Abbreviation R/W Initial Value Address
Access Size
Standby control register STBCR
R/W H'00*
H'FFFFFF82 Byte
Note: * Initialized by a power-on reset. In a manual reset, the register contents are retained.
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