SH7708 Datasheet, PDF (225/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bits 12 to 10—Area 5 Wait Control (A5W2, A5W1, A5W0): These bits specify the number of
wait states inserted in physical space area 5. They also specify the burst pitch for burst transfer.
Bit 12:
A5W2
0
1
Bit 11:
A5W1
0
1
0
1
Bit 10:
A5W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer
WAIT Pin
0
Ignored
2
Enabled
1
Enabled
2
Enabled
2
Enabled
3
Enabled
3
Enabled
4
Enabled
4
Enabled
4
Enabled
6
Enabled
6
Enabled
8
Enabled
8
Enabled
10 (Initial value) Enabled
10
Enabled
Bits 9 to 7—Area 4 Wait Control (A4W2, A4W1, A4W0): These bits specify the number of wait
states inserted in physical space area 4.
Bit 9: A4W2
0
1
Bit 8: A4W1
0
1
0
1
Bit 7: A4W0
0
1
0
1
0
1
0
1
Description
Inserted Wait States WAIT Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
4
Enabled
6
Enabled
8
Enabled
10
Enabled (Initial value)
207