SH7708 Datasheet, PDF (294/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Burst Access: In addition to the normal access mode in which CE is asserted and negated in each
access, some pseudo-SRAMs are provided with a static column mode for the case where
consecutive accesses are made to the same row address. This mode allows fast access to data by
keeping CE asserted and changing only the column address. Normal access or burst access using
static column mode can be selected by means of the burst enable (BE) bit in MCR. The timing for
burst access in static column mode is shown in figure 10.36. Cycles can also be inserted by the
wait state control function when burst access is performed.
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