SH7708 Datasheet, PDF (385/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 13.11 Serial Communication Formats (Asynchronous Mode)
SCSMR Bits
CHR PE MP STOP
0 00 0
Serial Transmit/Receive Format and Frame Length
1 2345678 9
10 11 12
S
8-bit data
STOP
0 00 1
S
8-bit data
STOP STOP
0 10 0
S
8-bit data
P STOP
0 10 1
S
8-bit data
P STOP STOP
1 00 0
S
7-bit data
STOP
1 00 1
S
7-bit data
STOP STOP
1 10 0
S
7-bit data
P STOP
1 10 1
S
7-bit data
P STOP STOP
0 —1 0
S
8-bit data
MPB STOP
0 —1 1
S
8-bit data
MPB STOP STOP
1 —1 0
S
7-bit data
MPB STOP
1 —1 1
S
Legend
— : Don’t care bits
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
7-bit data
MPB STOP STOP
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected
by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control
register (SCSCR) (table 13.10).
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as shown in figure 13.3
so that the rising edge of the clock occurs at the center of each transmit data bit.
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