SH7708 Datasheet, PDF (193/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

9.6 PLL Standby Function
9.6.1 Overview of the PLL Standby Function
When operating in clock modes 3 and 4, the internal clock can be controlled by turning the PLL1
circuit on and off. A long oscillation settling time is required, however, when the PLL circuit is
started up from a complete halt. During this time, processor operation halts. To enable fast on/off
switching of the PLL1 circuit, the PLL standby function is provided. This function is controlled by
software using the frequency control register. The use of the PLL standby function is described
below.
9.6.2 Usage
From Off to On:
1. Initially, PSTBY = 0, PLLEN = 0, and PLL circuit 1 is stopped. The output of PLL circuit 2 is
used for divider 1 input.
2. When the multiplication rate of PLL circuit 1 is set in the STC1–STC0 bits and PSTBY is set
to 1, PLL circuit 1 begins oscillating at the specified multiplication rate. The input to divider 1
is still the output of PLL circuit 2 at this point.
3. After PLL circuit 1 oscillation has stabilized, the input of divider 1 switches when PLLEN is
set to 1 and the oscillation output of PLL circuit 1 is divided and becomes the internal clock.
At this time, the division ratio can be changed by changing the settings of IFC1–IFC0 and
PFC1–PFC0. For several cycles before and after the clock switches, the internal clock will be
stopped, but the peripheral clock and CKIO output do not stop.
From On to Off:
1. When PLLEN is set to 0, the input of divider 1 switches to the output of PLL circuit 2. At this
time, the division ratio can be changed by changing the settings of IFC1–IFC0 and PFC1–
PFC0.
2. When PSTBY is set to 0, PLL circuit 1 stops. This setting can be performed simultaneously
(and with the same instruction as) the setting in 1 above.
Notes: 1. There are some restrictions on the PLL standby state (PSTBY = 1, PLLEN = 0) as
follows: The settings of the frequency control register’s CKOEN, STC2–STC0,
IFC2–IFC0 and PFC2–PFC0 bits generally cannot be changed. In some cases,
however, they can be changed if the PSTBY and PLLEN bit settings are also changed
simultaneously (figure 9.3). The SLEEP instruction cannot be executed.
2. It is the responsibility of software to ensure the oscillation settling time. If PLLEN is
set to 1 before the oscillation has settled, malfunctions may be caused by an unstable
clock.
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