SH7708 Datasheet, PDF (372/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, SCTDR did not contain valid data, so transmission has ended. TEND is a read-only
bit and cannot be written.
Bit 2: TEND
0
1
Description
Transmission is in progress.
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE, or data is written in SCTDR.
End of transmission.
(Initial value)
TEND is set to 1 when the chip is reset or enters standby mode, TE is cleared to
0 in the serial control register (SCSCR), or TDRE is 1 when the last bit of a one-
byte serial character is transmitted.
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when
a multiprocessor format is selected for receiving in asynchronous mode. MPB is a read-only bit
and cannot be written.
Bit 1: MPB
0
1
Description
Multiprocessor bit value in receive data is 0.
(Initial value)
If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains
its previous value.
Multiprocessor bit value in receive data is 1.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The
MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or
when the SCI is not transmitting.
Bit 0: MPBT
0
1
Description
Multiprocessor bit value in transmit data is 0.
Multiprocessor bit value in transmit data is 1.
(Initial value)
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