SH7708 Datasheet, PDF (303/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Memory Card Interface Basic Timing: Figure 10.42 shows the basic timing for the PCMCIA IC
memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface
areas, bus accesses are automatically performed as IC memory card interface accesses when the
lower address 32 Mbyte space of each area is accessed.
With a high external bus frequency (CKIO), the setup and hold times for the address (A24–A0),
card enable (CS5, CE2A, CS6, CE2B), and write data (D15–D0) in a write cycle, become
insufficient with respect to RD and WR (the WE1 pin in the SH7708 Series). The SH7708 Series
provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the
PCR register. Also, software waits by means of a WCR2 register setting and hardware waits by
means of the WAIT pin can be inserted in the same way as for the basic interface. WAIT is a
synchronous signal. Figure 10.43 shows the PCMCIA memory bus wait timing.
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