SH7708 Datasheet, PDF (324/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.2.3 Timer Control Register (TCR)
The timer control registers (TCR) control the timer counters (TCNT) and interrupts. The TMU has
three TCR, registers one for each channel.
The TCR registers are 16-bit read/write registers that control the issuance of interrupts when the
flag indicating timer counter (TCNT) underflow has been set to 1, and also carry out counter clock
selection. When the external clock has been selected, they also select its edge. Additionally, TCR2
controls the channel 2 input capture function and the issuance of interrupts during input capture.
The TCRs are initialized to H'0000 by a power-on reset and manual reset. In standby mode, when
the PLL1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the MSTP2 bit is
set to 1 in STBCR, the TCRs retain their contents when the input clock selected for the channel is
an external clock (TCLK) or the peripheral clock (Pø), and continue operating when the selected
clock is the on-chip RTC output clock (RTCCLK).
Channel 0 and 1 TCR Bit Configuration:
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
UNF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
Bit name: —
Initial value: 0
R/W: R
6
5
4
3
2
1
0
—
UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Channel 2 TCR Bit Configuration:
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
ICPF UNF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bit:
Bit name:
Initial value:
R/W:
7
ICPE1
0
R/W
6
ICPE0
0
R/W
5
UNIE
0
R/W
4
3
2
1
0
CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0
0
0
0
0
R/W R/W R/W R/W R/W
306