SH7708 Datasheet, PDF (516/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

17.3.1 Clock Timing
Table 17.5 Clock Timing (V_CC = 3.15Å–3.6 V, Ta = –20 to 75°C, Maximum External Bus
Operating Frequency: 60 MHz)
Item
Symbol Min
Max
EXTAL clock input frequency
fEX
5
60
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
tEXcyc
tEXL
tEXH
16.7
200
4*1 or 10*2 —
4*1 or 10*2 —
EXTAL clock input rise time
tEXr
—
2
EXTAL clock input fall time
tEXf
—
2
CKIO clock frequency (input)
fCKI
16
60
CKIO clock cycle time (input)
tCKIcyc
16.7
62.5
CKIO clock low-level pulse width (input)
tCKIL
4
—
CKIO clock high-level pulse width (input)
tCKIH
4
—
CKIO clock rise time (input)
tCKIr
—
2
CKIO clock fall time (input)
tCKIf
—
2
CKIO clock output frequency (output)
fOP
16
60
CKIO clock cycle time (output)
tcyc
16.7
62.5
CKIO clock low-level pulse width (output)
tCKOL
3
—
CKIO clock high-level pulse width (output)
tCKOH
3
—
CKIO clock rise time (output)
tCKOr
—
5
CKIO clock fall time (output)
tCKOf
—
5
Power-on oscillation settling time
tOSC1
10
—
Power-on oscillation settling time/mode setting tOSCMD 10
—
BREQ reset hold time
tBREQRH 0
—
RESET set-up time
tRESS
20
—
BREQ set-up time
tBREQS 20
—
MD reset hold time
tMDRH
20
—
Reset assert time
tRESW
20
—
Standby return oscillation settling time 1
tOSC2
10
—
Standby return oscillation settling time 2
tOSC3
10
—
Standby return oscillation settling time 3
tOSC4
11
—
PLL synchronization settling time
tPLL
100
—
IRL interrupt decision time (using RTC and in tIRLSTB 100
—
standby mode)
Notes: 1. PLL circuit 2 in operation.
2. IPLL circuit 2 not in operation.
Unit
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
tcyc
ms
ms
ms
µs
µs
Figure
17.1
17.2
17.3
17.4
17.4,
17.5,
17.11
17.5
17.6
17.7
17.8,
17.9,
17.10
17.10
498