SH7708 Datasheet, PDF (68/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

2.6 Usage Note
In the SH7708R, operations may not be performed correctly when the following sequences are
executed with the cache on.
Address Instruction
4n
MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L)
4n+2 MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L)
4n+4
or
STS(.L)/LDS(.L) MACH/MACL
4n+2
4n+4
MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L)
NOP (or one-cycle instruction except MAC instruction*¹ or branch
instruction*²)
4n+6 MAC.L (or MAC.W, DMULS.L, DMULU.L, MUL.L)
4n+8 STS(.L)/LDS(.L) MACH/MACL
Notes: 1. MULS.W, MULU.W, MAC.L, MAC.W, DMULS.L, DMULU.L, MUL.L, MULS.W,
MULU.W
2. BF, BF/S, BT, BT/S, BRA, BRAF, BSR, BSRF, JMP, JSR, RTS
Software Remedy: This problem can be avoided in either of the following ways.
1. Do not use the above sequences.
2. When performing STS/LDS on the MACL/MACH register after consecutive execution of MAC
instructions, insert an NOP instruction between the MAC instructions and STS/LDS
instruction.
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