SH7708 Datasheet, PDF (232/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.2.6 DRAM Control Register (DCR)
The DRAM area control register (DCR) is a 16-bit read/write register that specifies RAS and CAS
timing and burst control for DRAM connected to area 2. It also specifies address multiplexing and
controls refreshing. When DRAM is connected to area 2, the bus width is fixed at 16 bits. In such
cases, set the area 3 bus width to 16 bits as well. Other areas should be 8 bits or 16 bits. DCR is
initialized to H'0000 by a power-on reset, but is not initialized by a manual resets or in standby
mode. Do not access external memory outside area 2 until initialization of this register is
complete.
Bit: 15
14
13
12
11
Bit name: TPC1 TPC0 RCD1 RCD0 —
Initial value: 0
0
0
0
0
R/W: R/W R/W R/W R/W
R
10
9
8
— TRAS1 TRAS0
0
0
0
R
R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: —
BE
— AMX1 AMX0 RFSH RMODE —
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W
R
R/W R/W R/W R/W
R
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): These bits set the RAS precharge time for
the DRAM connected to area 2.
Bit 15: TPC1
0
1
Bit 14: TPC0
0
1
0
1
Normally
1 cycle (Initial value)
2 cycles
3 cycles
4 cycles
Description
Immediately after Self-Refresh
2 cycles (Initial value)
5 cycles
8 cycles
11 cycles
Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): These bits set the RAS–CAS delay time for
the DRAM connected to area 2.
Bit 13: RCD1
0
1
Bit 12: RCD0
0
1
0
1
Description
1 cycle
2 cycles
3 cycles
4 cycles
(Initial value)
214