SH7708 Datasheet, PDF (286/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in a manual
reset.
CKIO
TRs1 (TRs2)
(TRs2) TRs3 (Tpc) (Tpc)
CKE
CSn
RAS
CASxx
RD/WR
Figure 10.31 Synchronous DRAM Self-Refresh Timing
3. Relationship between refresh requests and bus cycle requests
If a refresh request is generated during execution of a bus cycle, execution of the refresh is
deferred until the bus cycle is completed. If a refresh request occurs when the bus has been
released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match
between RTCNT and RTCOR occurs while a refresh is waiting to be executed, thereby generating
a new refresh request, the previous refresh request is eliminated. To perform normal refreshing,
ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a
refresh request is generated, the IRQOUT pin is asserted (driven low). Therefore, normal
refreshing can be performed by having the IRQOUT pin monitored by a bus master other than the
SH7708 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7708 Series.
When refreshing is started, and if no other interrupt request has been generated, the IRQOUT pin
is negated (driven high).
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