SH7708 Datasheet, PDF (218/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.2 BSC Registers
10.2.1 Bus Control Register 1 (BCR1)
The bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus
cycle status for each area. It is initialized to H'0000 by a power-on reset, but is not initialized by a
manual reset or in standby mode. Do not access external memory outside area 0 until BCR1
register initialization is complete.
Bit: 15
Bit name: —
Initial value: 0
R/W: R
14
13
12
11
10
9
8
— HIZMEM*² HIZCNT ENDIAN A0BST1 A0BST0 A5BST1
0
0
0
0/1*¹
0
0
0
R
R/W R/W
R
R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: A5BST0 A6BST1 A6BST0 DRAM DRAM DRAM A5PCM A6PCM
TP2
TP1
TP0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Notes: 1. Samples the value of the external pin designating endian upon a power-on reset.
2. Reserved bit in the SH7708.
Bits 15 and 14—Reserved: These bits always read 0. The write value should always be 0.
Bits 13 (SH7708)—Reserved: These bits always read 0. The write value should always be 0. This
bit is not supported in emulator.
Bit 13 (SH7708S, SH7708R) —High-Z Memory Control (HIZMEM): Specifies the state of A25
to A0, BS, CS, RD/WR, WE/DQM, RD, MD3/CE2A, and MD4/CE2B in standby mode.
Bit 13: HIZMEM
0
1
Description
High-impedance (high-Z) in standby mode
Drive state in standby mode
(Initial value)
Bit 12—High-Z Control (HIZCNT): Specifies the state of the RAS and CAS signals in the standby
and bus-released states.
200