SH7708 Datasheet, PDF (461/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Stable input clock
EXTAL input
or CKIO input
PLL synchronization
PLL output,
CKIO output
Internal clock
IRL (3–0) interrupt request
Stable input clock
t_IRLSTB
t_PLL
PLL synchronization
STATUS 0
STATUS 1
Normal
Standby
Normal
Note: PLL oscillation settling time when clock is input from EXTAL pin or CKIO pin
Figure 16.9 PLL Synchronization Settling Time in Case of IRL Interrupt
EXTAL input or
on-chip
oscillator
output
CKOEN
CKIO
PLL synchronization
PLL1 output
tPLL
PLL synchronization
tPLL PLL synchronization
Internal clock
Note: PLL oscillation settling time when output clock is controlled by Clock Mode 0–2
Figure 16.10 PLL Synchronization Settling Time in Case of CKOEN Bit Manipulation
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