SH7708 Datasheet, PDF (234/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 1—Refresh Mode (RMODE): Selects the refresh mode for the DRAM connected to area 2.
Bit 1: RMODE
0
1
Description
CAS-before-RAS refresh (RFSH must be 1)
Self-refresh (RFSH must be 1)
(Initial value)
10.2.7 PCMCIA Control Register (PCR)
The PCMCIA control register (PCR) is a 16-bit read/write register that specifies the OE and WE
signal assert/negate timing for PCMCIA interfaces connected to areas 5 and 6. The OE and WE
signal assert pulse widths are designated by the WCR2 wait control bits. This register is initialized
to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode, and
retains its contents.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name: A5TED1 A5TED0 A6TED1 A6TED0 A5TEH1 A5TEH0 A6TEH1 A6TEH0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0.
Bits 7 and 6—Area 5 Address OE/WE Assert Delay (A5TED1, A5TED0): These bits specify the
address to OE/WE assert delay time for the PCMCIA interface connected to area 5.
Bit 7: A5TED1
0
1
Bit 6: A5TED0
0
1
0
1
Description
0.5 cycle delay
1.5 cycle delay
2.5 cycle delay
3.5 cycle delay
(Initial value)
216