SH7708 Datasheet, PDF (180/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

9.3 Clock Operating Modes
Table 9.3 shows the relationship between the mode control pin (MD2–MD0) combinations and the
clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes.
Table 9.3 Clock Operating Modes
Pin Values
Clock I/O
PLL2 Div- PLL1 Divider 1 Divider 2 CKIO
ModeMD2 MD1 MD0 Source Output On/Off ider 3 On/Off Input Input Frequency
0 0 0 0 EXTAL CKIO On
Off ON PLL1 PLL1 (EXTAL)
multi-
output
plication
ratio: 1
1 0 0 1 EXTAL CKIO On
Off ON PLL1 PLL1 (EXTAL)
multi-
output
×4
plication
ratio: 4
2 010
Crystal CKIO On
Off On
oscillator
multi-
plication
ratio: 4
PLL1
output
PLL1
(Crystal)
×4
3 0 1 1 EXTAL CKIO On
Off Off PLL2 PLL2 (EXTAL)
multi-
(initial output
×1
plication
value)
ratio: 1
On PLL1
output
4 1 0 0 Crystal CKIO On
Off Off PLL2 PLL2 (Crystal)
oscillator
multi-
(initial output
×1
plication
value)
ratio: 1
On PLL1
output
7 1 1 1 CKIO —
Off
Off On PLL1 PLL1 (CKIO)
output
Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by
PLL circuit 2 before being supplied inside the SH7708 Series. PLL circuit 1 is constantly on, and
there are no frequency range restrictions compared to mode 3. An input clock frequency of 8 MHz
to 60 MHz(SH7708, SH7708S) or 16 MHz to 60 MHz(SH7708R) can be used, and the CKIO
frequency range is 8 MHz to 60 MHz(SH7708, SH7708S) or 16 MHz to 60 MHz(SH7708R).
As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for
connection of synchronous DRAM.
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