SH7708 Datasheet, PDF (144/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

5. Sequential use of channels A and B is set in the SEQ bit of the BRCR. When sequential use is
designated, a user break occurs when the channel B conditions are matched after matching of
channel A conditions.
6. When a user break occurs, the CMFA and CMFB bits in the BRCR register are set to 1. If a
break is to be generated again, the CMFA and CMFB bits should be cleared to 0.
7.2 UBC Register Functions
7.2.1 Break Address Register A (BARA)
Bit:
Bit name:
Initial value:
R/W:
31
BAA31
—
R/W
30
BAA30
—
R/W
29
BAA29
—
R/W
28
BAA28
—
R/W
27
BAA27
—
R/W
26
BAA26
—
R/W
25
BAA25
—
R/W
24
BAA24
—
R/W
Bit:
Bit name:
Initial value:
R/W:
23
BAA23
—
R/W
22
BAA22
—
R/W
21
BAA21
—
R/W
20
BAA20
—
R/W
19
BAA19
—
R/W
18
BAA18
—
R/W
17
BAA17
—
R/W
16
BAA16
—
R/W
Bit:
Bit name:
Initial value:
R/W:
15
BAA15
—
R/W
14
BAA14
—
R/W
13
BAA13
—
R/W
12
BAA12
—
R/W
11
BAA11
—
R/W
10
BA10
—
R/W
9
BAA9
—
R/W
8
BAA8
—
R/W
Bit:
Bit name:
Initial value:
R/W:
7
BAA7
—
R/W
6
BAA6
—
R/W
5
BAA5
—
R/W
4
BAA4
—
R/W
3
BAA3
—
R/W
2
BAA2
—
R/W
1
BAA1
—
R/W
0
BAA0
—
R/W
Break address register A (BARA) is a 32-bit read/write register that stores the virtual address of
the channel A break condition. It is not initialized by a reset.
Bits 31 to 0—Break Address A31 to 0 (BAA31 to BAA0): These bits store the virtual address of
the channel A break condition.
7.2.2 Break Address Register B (BARB)
BARB is the break address register for channel B. The bit configuration is the same as for BARA.
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