SH7708 Datasheet, PDF (117/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

In RAM mode, two ways are used as cache (way 0 and way 1). Bit 5 of the LRU bits indicates
which way is to be replaced. When bit 5 is 0, way 1 is to be replaced. When bit 5 is 1, way 0 is to
be replaced.
The LRU bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
Table 5.2 LRU and Way Replacement in Normal Mode
LRU (5–0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
2
1
0
5.1.3 Register Configuration
Table 5.3 shows details of the cache control register.
Table 5.3 Register Configuration
Register
Abbr.
R/W Size
Cache control register
CCR
R/W Longword
Note: * Initialized by a power-on reset or manual reset.
Initial Value* Address
H'00000000 H'FFFFFFEC
5.2 Register Description
5.2.1 Cache Control Register (CCR)
The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also
has an RA bit (which switches the cache operation mode between RAM mode and normal mode),
a CF bit (which invalidates all cache entries), a WT bit and a CB bit* (which selects either write-
through mode or write-back mode). Programs that change the contents of the CCR register should
be placed in address space that is not cached. When updating the contents of the CCR register,
always set bit 4 to 0. Figure 5.2 shows the configuration of the CCR register. CB bit is not
supported in emulator.
Note: * SH7708S, SH7708R Only
99