SH7708 Datasheet, PDF (299/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

CKIO
T1
TW TW TB2 TB1 TW TB2 T2
T2
A25 to A4
A3 to A0
CSn
RD/WE
RD
D31 to
D0
BS
WAIT
Note: For a write cycle, a basic bus cycle (write cycle) is performed.
Figure 10.39 Burst ROM Wait Access Timing
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