SH7708 Datasheet, PDF (370/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 6—Receive Data Register Full (RDRF): Indicates that SCRDR contains received data.
Bit 6: RDRF Description
0
SCRDR does not contain valid received data.
(Initial value)
RDRF is cleared to 0 when the chip is reset or enters standby mode, software
reads RDRF after it has been set to 1, then writes 0 in RDRF, or data is read
from SCRDR.
1
SCRDR contains valid received data.
RDRF is set to 1 when serial data is received normally and transferred from
SCRSR to SCRDR.
Note:
SCRDR and RDRF are not affected by detection of receive errors or by clearing of the RE
bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set
to 1 when reception of the next data ends, an overrun error (ORER) occurs and the receive
data is lost.
Bit 5—Overrun Error (ORER): Indicates that data reception aborted due to an overrun error.
Bit 5: ORER
0
1
Description
Receiving is in progress or has ended normally.
(Initial value)
Clearing the RE bit to 0 in the serial control register does not affect the ORER bit,
which retains its previous value.
ORER is cleared to 0 when the chip is reset or enters standby mode or software
reads ORER after it has been set to 1, then writes 0 in ORER.
A receive overrun error occurred.
SCRDR continues to hold the data received before the overrun error, so
subsequent receive data is lost. Serial receiving cannot continue while ORER is
set to 1. In synchronous mode, serial transmitting is also disabled.
ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1.
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