SH7708 Datasheet, PDF (115/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Section 5 Cache
5.1 Overview
5.1.1 Features
The cache specifications are listed in table 5.1.
Table 5.1 Cache Specifications
Parameter
Capacity
Structure
Line size
Number of entries
Write system
Replacement method
Specification
Selectable: Normal mode: 8 kbytes
RAM mode: 4 kbytes cache and 4 kbytes RAM
Instruction/data mixed, 4-way set associative (2-way set associative in
RAM mode)
16 bytes
128 entries/way
P0, P1, P3, U0: Write-back/write-through selectable
Least-recently-used (LRU) algorithm
5.1.2 Cache Structure
The cache mixes data and instructions and uses a 4-way set associative system. It is composed of
four ways (banks), each of which is divided into an address section and a data section. Each of the
address and data sections is divided into 128 entries. The data section of the entry is called a line.
Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 2 kbytes (16 bytes × 128
entries), with a total of 8 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache
structure.
97