SH7708 Datasheet, PDF (279/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Single Read: Figure 10.26 shows the timing when a single address read is performed. As the burst
length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is
output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is
accessed.
Tr
CKIO
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
Tc1
Td1
Tpc
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
Figure 10.26 Basic Timing for Synchronous DRAM Single Read
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