SH7708 Datasheet, PDF (422/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bits 3 to 0: These bits have the same function as in the ordinary SCI. See section 13, Serial
Communication Interface, for more information. The setting conditions for bit 2, the transmit end
bit (TEND), are changed as follows.
Bit 2: TEND Description
0
Transmission is in progress.
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE, or when data is written in SCTDR.
1
End of transmission.
(Initial value)
TEND is set to 1 when:
• the chip is reset or enters standby mode,
• the TE bit in SCSCR is 0 and the FER/ERS bit is also 0,
• the C/A bit in SCSMR is 0, and TDRE = 1 and FER/ERS = 0 (normal
transmission) 2.5 etu after a one-byte serial character is transmitted, or
• the C/A bit in SCSMR is 1, and TDRE = 1 and FER/ERS = 0 (normal
transmission) 1.0 etu after a one-byte serial character is transmitted.
Note: etu is an abbreviation of elementary time unit, which is the period for the transfer of 1 bit.
14.3 Operation
14.3.1 Overview
The primary functions of the smart card interface are described below.
1. Each frame consists of 8 data bits and 1 parity bit.
2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: the
period for 1 bit to transfer) from the end of the parity bit to the start of the next frame.
2. During reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed
from the start bit if a parity error was detected.
4. During transmission, it automatically transmits the same data after allowing at least 2 etu from
the time the error signal is sampled.
5. The specification complies with ISO/ICE7816-3, but the only type of data transmission
protocol supported is protocol type T = 0 : asynchronous double-character transmission
protocol.
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