SH7708 Datasheet, PDF (412/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

13.4 SCI Interrupt Sources
The SCI has four interrupt sources in each channel: transmit-end (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty (TXI). Table 13.13 lists the interrupt sources and
indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE
bits in the serial control register (SCSCR). Each interrupt request is sent separately to the interrupt
controller.
TXI is requested when the TDRE bit in SCSSR is set to 1. TDRE is automatically cleared to 0
when data is written in the transmit data register (SCTDR).
RXI is requested when the RDRF bit in SCSSR is set to 1. RDRF is automatically cleared to 0
when the receive data register (SCRDR) is read.
ERI is requested when the ORER, PER, or FER bit in SCSSR is set to 1.
TEI is requested when the TEND bit in SCSSR is set to 1. Where the TXI interrupt indicates that
transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete.
Table 13.13 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
Description
Receive error (ORER, PER, or FER)
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
Priority When Reset Is Cleared
High
↓
Low
See section 4, Exception Handling, for information on the priority order and relationship to non-
SCI interrupts.
13.5 Usage Notes
Note the following points when using the SCI.
SCTDR Write and TDRE Flags: The TDRE bit in the serial status register (SCSSR) is a status
flag indicating loading of transmit data from SCTDR into SCTSR. The SCI sets TDRE to 1 when
it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE
bit status. If new data is written in SCTDR when TDRE is 0, however, the old data stored in
SCTDR will be lost because the data has not yet been transferred to SCTSR. Before writing
transmit data to SCTDR, be sure to check that TDRE is set to 1.
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