SH7708 Datasheet, PDF (106/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

4.2.6 Returning from Exception Handling
The RTE instruction is used to return from exception handling. When RTE is executed, the SPC
value is set in the PC, and the SSR value in SR, and the return from exception handling is
performed by branching to the SPC address.
If the SPC and SSR have been saved in external memory, set the BL bit in SR to 1, then restore
the SPC and SSR, and issue an RTE instruction.
4.3 Register Description
There are three registers related to exception handling. These are peripheral module registers, and
therefore reside in area P4. They can be accessed by specifying the address in privileged mode
only.
1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit
exception code. The exception code set in EXPEVT is that for a reset or general exception
event. The exception code is set automatically by hardware when an exception occurs.
EXPEVT can also be modified by software.
2. The interrupt event register (INTEVT) resides at address H'FFFFFFD8, and contains a 12-bit
exception code. The exception code set in EXPEVT is that for an interrupt request. The
exception code is set automatically by hardware when an exception occurs. INTEVT can also
be modified by software.
3. The TRAPA exception register (TRA) resides at address H'FFFFFFD0, and contains 8-bit
immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when
a TRAPA instruction is executed. TRA can also be modified by software.
The bit configurations of the EXPEVT, INTEVT, and TRA registers are shown in figure 4.3.
EXPEVT register and INTEVT register
31
11
0
0
0 Exception code
TRA register
31
0
0: Reserved bits, always read as zero
imm: 8-bit immediate data in TRAPA instruction
9
20
0 imm 00
Figure 4.3 Bit Configurations of EXPEVT, INTEVT, and TRA Registers
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