SH7708 Datasheet, PDF (121/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

PA (31–4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31–4): Physical address written to external memory
Longword 0–3: The line of cache data to be written to
external memory
Figure 5.4 Write-Back Buffer Configuration
5.3.5 Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory
shared by the SH7708 Series and another device is accessed, the latest data may be in a write-back
mode cache, so invalidate the entry that includes the latest data in the cache, generate a write back,
and update the data in memory before using it. When the caching area is updated by a device other
than the SH7708 Series, invalidate the entry that includes the updated data in the cache.
5.3.6 RAM Mode
In RAM mode, way 0 and way 1 function as a 4-kbyte two-way set associative cache, while way 2
and way 3 function as 4-kbyte internal RAM. The internal RAM is mapped onto H'7F000000 to
H'7F000FFF with 4-kbyte shadow areas from H'7F001000 to H'7FFFFFFF. In RAM mode with
the MMU enabled, a virtual address from H'7F00000 to H'7FFFFFFF is not translated to an
external physical address. The internal RAM can be accessed in both privileged and user mode by
setting its address as source or destination address in the instructions. Before changing the RA bit
in the CCR register to change the cache operation mode, all entries in the cache should be
invalidated.
5.4 Memory-Mapped Cache
To allow software management of the cache, it is mapped onto virtual address space P4. The
address array is mapped onto addresses H'F0000000 to H'F0FFFFFF and the data array onto
addresses H'F1000000 to H'F1FFFFFF. In privileged mode, the cache contents can be read or
written using the MOV instruction. With the address array and data array, the access size is fixed
at longword, and instruction fetches cannot be performed.
5.4.1 Address Array
The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the
32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the address, V bit, U bit, and LRU bits to be written to the address array (figure
5.5 (1)).
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