SH7708 Datasheet, PDF (205/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Section 10 Bus State Controller (BSC)
10.1 Overview
The bus state controller (BSC) divides physical address space and outputs control signals for
various types of memory and bus interface specifications. BSC functions enable the SH7708
Series to link directly with DRAM, synchronous DRAM, pseudo-SRAM, SRAM, ROM, and other
memory storage devices without an external circuit. The BSC also allows direct connection to
PCMCIA interfaces, simplifying system design and allowing high-speed data transfers in a
compact system.
10.1.1 Features
The BSC has the following features:
• Physical address space is divided into seven areas
 A maximum 64 Mbytes for each of the seven areas, 0–6
 Area bus width can be selected by register (area 0 is set by external pin)
 Wait states can be inserted using the WAIT pin
 Wait state insertion can be controlled through software. Register settings can be used to
specify the insertion of 1–10 cycles independently for each area (areas 1 and 2 have a
common setting)
 The type of memory connected can be specified for each area, and control signals are
output for direct memory connection
 Wait cycles are automatically inserted to avoid data bus conflict for continuous memory
accesses to different areas or writes directly following reads of the same area
• Direct interface to DRAM
 Multiplexes row/column addresses according to DRAM capacity
 Supports burst operation (high-speed page mode, hyper page mode)
 Supports CAS-before-RAS refresh and self-refresh
 Performs low power 4-CAS-system byte control
 Controls timing of DRAM direct-connection control signals according to register settings
• Direct interface to synchronous DRAM
 Multiplexes row/column addresses according to synchronous DRAM capacity
 Supports burst operation
 Has both auto-refresh and self-refresh functions
 Controls timing of synchronous DRAM direct-connection control signals according to
register setting
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