SH7708 Datasheet, PDF (224/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.2.4 Wait State Control Register 2 (WCR2)
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in
standby mode, but retains its contents.
Bit:
Bit name:
Initial value:
R/W:
15
A6W2
1
R/W
14
A6W1
1
R/W
13
A6W0
1
R/W
12
A5W2
1
R/W
11
A5W1
1
R/W
10
A5W0
1
R/W
9
A4W2
1
R/W
8
A4W1
1
R/W
Bit:
Bit name:
Initial value:
R/W:
7
A4W0
1
R/W
6
A3W1
1
R/W
5
A3W0
1
R/W
4
3
A1-2W1 A1-2W0
1
1
R/W R/W
2
A0W2
1
R/W
1
A0W1
1
R/W
0
A0W0
1
R/W
Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): These bits specify the number of
wait states inserted in physical space area 6. They also specify the burst pitch for burst transfer.
Bit 15:
A6W2
0
1
Bit 14:
A6W1
0
1
0
1
Bit 13:
A6W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer
WAIT Pin
0
Ignored
2
Enabled
1
Enabled
2
Enabled
2
Enabled
3
Enabled
3
Enabled
4
Enabled
4
Enabled
4
Enabled
6
Enabled
6
Enabled
8
Enabled
8
Enabled
10 (Initial value) Enabled
10
Enabled
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