SH7708 Datasheet, PDF (161/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

8.1.3 Pin Configuration
Table 8.3 lists the pins used for the power-down modes.
Table 8.3 Pin Configuration
Processing
Status 1 Pin (STATUS1)
Processing
Processor
Status 0 Pin (STATUS0)
I/O
Operating Status
High
High
O
Reset
Low
Sleep mode
Low
High
Standby mode
Low
Normal operation
Note: The “normal operation” status applies during refresh cycles even in sleep mode.
8.2 Register Description
8.2.1 Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit read/write register that sets the power-down
mode. STBCR is initialized to H'00 by a power-on reset. Always set bits 6–3 to 0 when writing to
the STBCR register.
Bit: 7
6
5
4
3
2
1
0
Bit name: STBY
—
—
—
— MSTP2 MSTP1 MSTP0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R/W R/W R/W
Bit 7—Standby (STBY): Specifies transition to standby mode.
Bit 7: STBY
0
1
Description
Executing SLEEP instruction puts the chip into sleep mode. (Initial value)
Executing SLEEP instruction puts the chip into standby mode.
Bits 6 to 3—Reserved: These bits always read 0. The write value should always as 0.
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