M32C8A Datasheet, PDF (99/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
9. Clock Generation Circuits
Table 9.3 Bit Settings to Use PLL Clock as CPU Clock Source
Multiplication
factor
PLC02 bit
PLC0 Register
PLC01 bit
PLC00 bit
PLC1 Register
PLC12 bit
2
1
3
0
1
1
0
8/3
1
4
1
0
0
0
PLL Clock
fPLL = 2 × fXIN
fPLL = 3 × fXIN
fPLL = 8/3 × fXIN
fPLL = 4 × fXIN
Start
PRCR register: PRC0 bit = 1
CM2 register: CM21 bit = 0
CM0 register: CM07 bit = 0
Set registers PLC0 and PLC1
PLC0 register: PLC07 bit = 1
Wait for tsu(PLL)
CM1 register : CM17 bit = 1
PRC0 bit = 0
End
Enable writing to registers associated with clocks
Select the main clock as the CPU clock source
(※Set after a main clock oscillation stabilizes)
Select the multiplication factor for the PLL clock
(※Set registers PLC0 and PLC1 simultaneously in 16-bit units)
　 PLC1 PLC0 Multiplication factor for PLL clock
00000010 01010011b × 6/2 = 3
00000010 01010100b × 8/2 = 4
00000110 01010011b × 6/3 = 2
00000110 01010100b × 8/3 = 2.66
PLL runs
Wait for PLL frequency synthesizer to stabilize
Select the PLL clock as the clock source for the CPU clock
and peripheral function clock
Disable writing to registers associated with clocks
Figure 9.12 Procedure to Use PLL Clock as CPU Clock Source
Rev.1.00 Jul 15, 2007 Page 82 of 352
REJ09B0385-0100