M32C8A Datasheet, PDF (124/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
11. Interrupts
11.6.4 Interrupt Response Time
Figure 11.7 shows the interrupt response time. Interrupt response time is the period between an interrupt
request generation and the end of an interrupt sequence. Interrupt response time is divided into two phases: the
period between an interrupt request generation and the end of the ongoing instruction execution ((a) in Figure
11.7), and the period required to perform the interrupt sequence ((b) in Figure 11.7).
Interrupt request is
generated
Interrupt request is
acknowledged
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Time
Instruction in interrupt routine
(a) Period between an interrupt request generation and the end of instruction execution.
(b) Period required to perform an interrupt sequence.
Figure 11.7 Interrupt Response Time
Time (a) varies depending on an instruction being executed. The DIV, DIVX, and DIVU instructions require
the longest time (a), which is at the maximum of 42 cycles.
Table 11.5 lists time (b).
Table 11.5 Interrupt Sequence Execution Time⁽¹⁾
Interrupts
Execution Time
(in terms of CPU clock)
Peripheral function
16 cycles
INT instruction
14 cycles
NMI
Watchdog timer
Undefined instruction
Address match
15 cycles
Overflow
16 cycles
BRK instruction (relocatable vector table)
19 cycles
BRK instruction (fixed vector table)
21 cycles
High-speed interrupt
5 cycles
NOTE:
1. The values when interrupt vectors are allocated in even addresses in the external ROM, and when the external
bus cycle is two CPU clock cycles. This does not apply to the high-speed interrupt.
Rev.1.00 Jul 15, 2007 Page 107 of 352
REJ09B0385-0100