M32C8A Datasheet, PDF (72/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
8. Bus
8.2.4 Bus Timing
Software wait states for the internal RAM can be set using the PM12 bit in the PM1 register, for the SFR area
using the PM13 bit, and for external spaces using the EWCRi register (i = 0 to 3). Table 8.6 lists a software
wait state and bus cycle.
The basic bus cycle for the internal RAM and SFR area is one bus clock (BCLK) cycle. A read or write to the
internal RAM takes the basic bus cycle. When the PM12 bit in the PM1 register to 1 (1 wait state), an access to
the internal RAM takes two BCLK cycles.
A read or write to the SFR area takes two BCLK cycles (1 wait state). When the PM13 bit in the PM1 register
is set to 1 (2 wait states), an access takes three BCLK cycles.
The external bus cycle is divided into two phases: the number of BCLK cycles in the period from the beginning
of the bus access until the read or write output signal becomes “L” (first φ), and the number of BCLK cycles in
the period from the read or write output signal becomes “L” until the signal changes to “H” (second φ).
The minimum read or write cycle for the external bus is two BCLK clock cycles (1 φ + 1 φ). The EWCRi
register (i = 0 to 3) selects an external bus cycle from 12 types for the separate bus and seven types for the
multiplexed bus. For example, when bits EWCRi4 to EWCRi0 in the EWCRi register are set to 00011b
(1 φ+3 φ), the external bus cycle is four BCLK cycles.
Figure 8.3 shows the EWCRi register. Figures 8.4 to 8.8 show external bus timings.
External Space Wait Control Register i (i = 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
EWCR0 to EWCR3
Address
0048h, 0049h, 004Ah, 004Bh
After Reset
X0X0 0011b
Bit Symbol
Bit Name
Function
RW
EWCRi0
EWCRi1
EWCRi2 Bus cycle select bits⁽³⁾
EWCRi3
EWCRi4
b4 b3 b2 b1 b0 (1) (2)
0 0 0 0 1: 1 φ + 1 φ
RW
0 0 0 1 0: 1 φ + 2 φ
0 0 0 1 1: 1 φ + 3 φ
0 0 1 0 0: 1 φ + 4 φ
RW
0 0 1 0 1: 1 φ + 5 φ
0 0 1 1 0: 1 φ + 6 φ
0 1 0 1 0: 2 φ + 2 φ
0 1 0 1 1: 2 φ + 3 φ
RW
0 1 1 0 0: 2 φ + 4 φ
0 1 1 0 1: 2 φ + 5 φ
1 0 0 1 1: 3 φ + 3 φ
RW
1 0 1 0 0: 3 φ + 4 φ
1 0 1 0 1: 3 φ + 5 φ
1 0 1 1 0: 3 φ + 6 φ
RW
Do not set to values other than the above
−
Unimplemented.
(b5)
Write 0. Read as undefined value.
−
EWCRi6
Recovery cycle insert
select bit
0: Insert no recovery cycle when accessing
external space i
1: Insert a recovery cycle when accessing
RW
external space i
−
Unimplemented.
(b7)
Write 0. Read as undefined value.
−
NOTES:
1. The number of BCLK cycles in the period from the beginning of the bus access until the read or write output signal becomes "L".
2. The number of BCLK cycles in the period from the read or write output signal becomes "L" until the signal changes to "H".
Figure 8.3 EWCR0 to EWCR3 Registers
Rev.1.00 Jul 15, 2007 Page 55 of 352
REJ09B0385-0100