M32C8A Datasheet, PDF (155/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
14. DMACII
14.3.2 Immediate Data Transfer
DMACII transfers immediate data to a given memory location. A fixed or incremented address can be selected
as a destination address. Store immediate data into SADR. To transfer an 8-bit immediate data, write data in the
low-order byte of SADR. (The high-order byte is ignored.)
14.3.3 Calculation Transfer
After two memory data, or an immediate data and a memory data, are added together, DMACII transfers the
calculated result to a given memory location. Set a memory address or immediate data to be calculated in
SADR. Set another memory address to be calculated in OADR. To use a “memory + memory” calculation
transfer, a fixed or incremented address can be selected as a source or destination address. If a source address is
incremented, an operation address also becomes incremented. To use an “immediate data + memory”
calculation transfer, a fixed or incremented address can be selected as a destination address.
14.4 Transfer Modes
In DMACII, a single transfer, burst transfer, and multiple transfer are available. The BRST bit in MOD selects
either a single transfer or burst transfer, and the MULT bit in MOD selects a multiple transfer. COUNT determines
how many transfers occur. No transfer occurs when COUNT is set to 0000h.
14.4.1 Single Transfer
For one transfer request, DMACII transfers an 8-bit or 16-bit data once. When an incremented address is
selected for a source or destination address, DMACII increments the address after every transfer for the
following transfer.
COUNT is decremented every time a transfer occurs. If using the end-of-transfer interrupt, an interrupt occurs
when COUNT reaches zero.
14.4.2 Burst Transfer
For one transfer request, DMACII continuously transfers data the number of times determined by COUNT.
COUNT is decremented every time DMACII transfers one transfer unit, and when it reaches zero, a burst
transfer is completed. If using the end-of-transfer interrupt, an interrupt occurs at the end of the burst transfer.
While the burst transfer is taking place, no interrupt can be acknowledged.
14.4.3 Multiple Transfer
When using the multiple transfer, select the memory-to-memory transfer. For one transfer request, DMACII
transfers data multiple times. Bits CNT2 to CNT0 in MOD selects the number of transfers from 001b (once) to
111b (7 times). Do not set bits CNT2 to CNT0 to 000b.
Source and destination addresses enough for all transfers must be allocated alternately in addresses following
MOD and COUNT in DMACII index.
While the transfers are taking place the number of times set using bits CNT2 to CNT0, no interrupt can be
acknowledged. When the multiple transfer is selected, a calculation transfer, burst transfer, chain transfer, and
end-of-transfer interrupt cannot be used.
Rev.1.00 Jul 15, 2007 Page 138 of 352
REJ09B0385-0100