M32C8A Datasheet, PDF (119/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
11. Interrupts
11.6 Interrupt Request Acknowledgement
Software interrupts occur when their corresponding instructions are executed. The INTO instruction, however,
requires the O flag in the FLG register to be 1. Special interrupts occur when their corresponding interrupt requests
are generated.
For the peripheral function interrupts to be acknowledged, the following conditions must be met:
• I flag = 1
• IR bit = 1
• Bits ILVL2 to ILVL > IPL
The I flag, IPL, IR bit, and bits ILVL2 to ILVL0 are independent of each other. The I flag and IPL are in the FLG
register. The IR bit and bits ILVL2 to ILVL0 are in the Interrupt Control Register.
11.6.1 I Flag and IPL
The I flag enables and disables maskable interrupts. When the I flag is set to 1 (enable), all maskable interrupts
are enabled; when the I flag is set to 0 (disable), they are disabled. The I flag is automatically set to 0 after
reset.
IPL is 3 bits wide and indicates the Interrupt Priority Level (IPL) from level 0 to level 7. If a requested interrupt
has higher priority level than IPL, the interrupt is acknowledged.
Table 11.4 lists interrupt priority levels associated with IPL.
Table 11.4 Interrupt Priority Levels
IPL2 to IPL0
Required Interrupt Priority Levels to Be Acknowledged
for Maskable Interrupts
0
Level 1 and above
1
Level 2 and above
2
Level 3 and above
3
Level 4 and above
4
Level 5 and above
5
Level 6 and above
6
Level 7 and above
7
All maskable interrupts are disabled
11.6.2 Interrupt Control Registers and RLVL Register
The Interrupt Control Registers are used to control the peripheral function interrupts. Figures 11.4 and 11.5
show the Interrupt Control Registers. Figure 11.6 shows the RLVL register.
Rev.1.00 Jul 15, 2007 Page 102 of 352
REJ09B0385-0100