M32C8A Datasheet, PDF (159/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
15. Timers
TB0IN
TB1IN
TB2IN
TB3IN
TB4IN
TB5IN
XCIN
Clock prescaler
1/32
Set the CPSR bit in the
CPSRF register to 1
Reset
f1 f8 f2n fC32
Timer B2 overflow or underflow signal
(to the count source of timer A)
00 ^{TCK1 and TCK0}
01
10
11
Noise
filter
00 ^{TCK1 and TCK0}
01
10
11
Noise
filter
00 ^{TCK1 and TCK0}
01
10
11
Noise
filter
00 ^{TCK1 and TCK0}
01
10
11
Noise
filter
00 ^{TCK1 and TCK0}
01
10
11
Noise
filter
TCK1 and TCK0
00
01
10
11
Noise
filter
1
0
TCK1
1
0
TCK1
1
0
TCK1
1
0
TCK1
1
0
TCK1
1
0
TCK1
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
Timer B0
01: Event counter mode
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
Timer B1
01: Event counter mode
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
Timer B2
01: Event counter mode
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
Timer B3
01: Event counter mode
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
Timer B4
01: Event counter mode
TMOD1 and TMOD0
00: Timer mode
10: Pulse width measurement mode,
Pulse cycle measurement mode
Timer B5
01: Event counter mode
fC32
Timer B0 interrupt
Timer B1 interrupt
Timer B2 interrupt
Timer B3 interrupt
Timer B4 interrupt
Timer B5 interrupt
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register (i = 0 to 5)
Figure 15.2 Timer B Configuration
Rev.1.00 Jul 15, 2007 Page 142 of 352
REJ09B0385-0100