M32C8A Datasheet, PDF (137/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
13. DMAC
13. DMAC
DMAC allows data to be sent to and from memory without involving the CPU. The M32C/8A Group has four DMAC
channels. DMAC transfers a 8- or 16-bit data from a source address to a destination address for each transfer request.
DMA0 and DMA1 must be prioritized when using DMAC. DMA2 and DMA3 share the registers with the high-speed
interrupts. The high-speed interrupts cannot be used when three or more DMAC channels are used.
The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU. DMAC
employing the cycle-steal method enables a high-speed operation from a transfer request to a completion of 16-bit
(word) or 8-bit (byte) data transfer.
Figure 13.1 shows a mapping of DMAC-associated registers. Table 13.1 lists specifications of DMAC. Figures 13.2
to 13.6 show DMAC-associated registers. Figures 13.7 and 13.8 show register settings.
Because the registers shown in Figure 13.1 are allocated in the CPU, use the LDC instruction to set the registers.
To set registers DCT2, DCT3, DRC2, DRC3, DMA2, and DMA3, set the B flag to 1 (register bank 1) and write to
registers R0 to R3, A0, and A1 with the MOV instruction.
To set registers DSA2 and DSA3, set the B flag to 1 and write to registers SB and FB with the LDC instruction.
To set registers DRA2 and DRA3, write to registers SVP and VCT with the LDC instruction.
DMAC-Associated Registers
DMD0
DMD1
DCT0
DCT1
DRC0
DRC1
DMA0
DMA1
DSA0
DSA1
DRA0
DRA1
DMA mode register 0
DMA mode register 1
DMA0 transfer count register
DMA1 transfer count register
DMA0 transfer count reload register⁽¹⁾
DMA1 transfer count reload register⁽¹⁾
DMA0 memory address register
DMA1 memory address register
DMA0 SFR Address register
DMA1 SFR Address register
DMA0 memory address reload register⁽¹⁾
DMA1 memory address reload register⁽¹⁾
When three or more DMAC channels are used,
the register bank 1 is employed as DMAC registers.
When three or more DMAC channels are used,
the high-speed interrupt registers are employed as DMAC
registers.
DCT2(R0)
DCT3(R1)
DRC2(R2)
DRC3(R3)
DMA2(A0)
DMA3(A1)
DSA2(SB)
DSA3(FB)
DMA2 transfer count register
DMA3 transfer count register
DMA2 transfer count reload register⁽¹⁾
DMA3 transfer count reload register⁽¹⁾
DMA2 memory address register
DMA3 memory address register
DMA2 SFR Address register
DMA3 SFR Address register
SVF
DRA2(SVP)
DRA3(VCT)
Flag save register
DMA2 memory address reload register⁽¹⁾
DMA3 memory address reload register⁽¹⁾
When using DMA2 and DMA3, use the CPU registers shown in
parentheses ( ).
NOTE:
1. These registers are used for repeat transfer, not for single transfer.
Figure 13.1 Register Mapping for DMAC
Rev.1.00 Jul 15, 2007 Page 120 of 352
REJ09B0385-0100