M32C8A Datasheet, PDF (131/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
11. Interrupts
11.8 NMI Interrupt
The NMI interrupt is non-maskable. The NMI interrupt occurs when a signal applied to the P8_5/NMI pin changes
from “H” level to “L” level. A read from the P8_5 bit in the P8 register returns the input level of the NMI pin.
When the NMI interrupt is not used, connect the NMI pin to VCC1 via a resistor (pull-up). “H” level or “L” level
width of the signal applied to the NMI pin must be 2 CPU clock cycles + 300 ns or more.
11.9 Key Input Interrupt
The IR bit in the KUPIC register becomes 1 when an falling edge is detected at any of the pins P10_4 to P10_7 set
to input mode. The key input interrupt can also be used as key-on wake-up function to exit wait mode or stop
mode. To use the key input interrupt, do not use pins P10_4 to P10_7 as A/D input. Figure 11.13 shows a block
diagram of the key input interrupt. When an “L” signal is applied to one of the pins P10_4 to P10_7 in input mode,
an falling edge detected at the other pins is not recognized as an interrupt request signal.
When the PSC_7 bit in the PSC register is set to 1 (AN_4 to AN_7), the input buffer for ports or the key input
interrupt is disconnected. Therefore, the pin level cannot be obtained by reading the Port P10 register in input
mode. Also, the IR bit in the KUPIC register does not become 1 even if a falling edge is detected at pins KI0 to
KI3.
Pull-up
transistor
PSC_7 bit
P10_7/KI3
P10_6/KI2
Pull-up
transistor
P10_5/KI1
Pull-up
transistor
P10_4/KI0
Pull-up
transistor
PU31 bit
PD10_7 bit
PD10_7 bit
PD10_6 bit
PD10_5 bit
PD10_4 bit
Figure 11.13 Key Input Interrupt
Key input interrupt request
PD10_4 to PD10_7: Bits in the PD10 register
PSC_7: Bit in the PSC register
PU31: Bit in the PUR3 register
Rev.1.00 Jul 15, 2007 Page 114 of 352
REJ09B0385-0100