M32C8A Datasheet, PDF (252/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
17.1.3.6 SDA Input
When the IICM2 bit in the UiSMR2 register (i = 0 to 4) is set to 0, the first eight bits of received data are stored
into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK.
When the IICM2 bit is set to 1, the first seven bits (D7 to D1) of received data are stored into bits 6 to 0 in the
UiRB register. The eighth bit (D0) is stored into bit 8 in the UiRB register.
If the IICM2 bit is set to 1 and the CKPH bit in the UiSMR3 register is set to 1 (clock delay), the same data as
that of when setting the IICM2 bit to 0 can be returned, by reading the UiRB register after the rising edge of the
ninth bit of the serial clock.
17.1.3.7 ACK, NACK
When the STSPSEL bit in the UiSMR4 register is set to 0 (start/stop condition not output) and the ACKC bit in
the UiSMR4 register is set to 1 (ACK data output), the SDAi pin outputs the setting value, ACK or NACK, of
the ACKD bit in the UiSMR4 register.
If the IICM2 bit is set to 0, the NACK interrupt request is generated when the SDAi pin is held high (“H”) at the
rising edge of the ninth bit of the serial clock. The ACK interrupt request is generated when the SDAi pin is
held low (“L”) at the rising edge of the ninth bit of the serial clock.
When ACK is selected to generate a DMA request source, the DMA transfer is activated by an ACK detection.
17.1.3.8 Transmit and Receive Operation Initialization
The following occurs when the STC bit in the UiSMR2 register is set to 1 (UARTi initialized) and the start
condition is detected:
• The UARTi transmit shift register is initialized and the contents of the UiTB register are transferred to the
UARTi transmit shift register. Then, the transmit operation is started at the next serial clock input to the
SCLi pin. UARTi output value remains the same as when the start condition was detected until the first bit
data is output.
• The UARTi receive shift register is initialized and the receive operation is started at the next serial clock
input to the SCLi pin.
• The SWC bit in the UiSMR2 register becomes 1 (SCLi pin is held “L” after receiving 8th bit). An output
from the SCLi pin becomes “L” at the falling edge of the ninth bit of the serial clock.
When UARTi transmit/receive operation is started with setting the STC bit to 1, the TI bit in the UiC1 register
remains unchanged. Also, select the external clock as the serial clock to start UARTi transmit/receive operation
with setting the STC bit to 1.
Rev.1.00 Jul 15, 2007 Page 235 of 352
REJ09B0385-0100