M32C8A Datasheet, PDF (191/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
15. Timers (Timer B)
15.2.2 Event Counter Mode
In event counter mode, the timer counts overflows/underflows of another timer, or the external pulses.
Table 15.10 lists specifications of event counter mode. Figure 15.28 shows an event counter mode operation.
Table 15.10 Specifications of Event Counter Mode
Item
Specification
Count source
• External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected
by program)
• TBj overflows or underflows (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3)
Count operation
• Counter decrements
When the timer underflows, the contents of the reload register are reloaded into
the counter and the count continues.
Number of counting
(n + 1) times
n: Setting value of the TBi register 0000h to FFFFh
Count start condition
The TBiS bit in the TABSR or TBSR register is set to 1 (count starts)
Count stop condition
The TBiS bit is set to 0 (count stops)
Interrupt request generation timing When the timer underflows
TBiIN pin function
Count source input
Read from timer
A read from the TBi register returns a counter value.
Write to timer
• A write to the TBi register while the count is stopped:
The value is written to both the reload register and the counter.
• A write to the TBi register while counting:
The value is written to the reload register (It is transferred to the counter at the
next reload timing).⁽¹⁾
NOTE:
1. Wait for one count source cycle or more to write after the count starts.
FFFFh
n
Count starts
Contents of the counter
n = contents of the reload
register
Underflow
Reload
Count resumes
Count stops
0000h
“H”
Input to the TBiIN pin
“L”
TBiS bit in the TABSR or TBSR ¹
regsiter
0
1
IR bit in the TBiIC regsiter
0
i = 0 to 5
Set to 0 by an interrupt request acknowledgement or by program
(Condition) TBiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode)
Bits MR1 and MR0 are set to 00b (count the falling edge of the external signal)
The TCK1 bit is set to 0 (signal input to TBiIN pin)
Figure 15.28 Operation in Event Counter Mode (Timer B)
Rev.1.00 Jul 15, 2007 Page 174 of 352
REJ09B0385-0100