M32C8A Datasheet, PDF (53/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
5. Reset
5.5 Internal Registers
Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Registers (SFRs) for SFR states
after reset.
General registers
0: 0 after reset
X: Undefined after reset
b15
b0
Flag register (FLG)
b15
b8 b7
b0
X0 0 0XXXX0 0 0 0 0 0 0 0
IPL
U I OBSZDC
High-speed interrupt registers
b15
b0
b23
XXXXh
Flag save register (SVF)
XXXXXXh
PC save register (SVP)
XXXXXXh
Vector register (VCT)
b15
b0
0_R0h_0H 0_R0h_{0L Data register (R0H/R0L)}
0_R0h_1H 0_R0h_{1L Data register (R1H/R1L)}
000_R0h₂
Data register (R2)
b23
000_R0h₃
Data register (R3)
0000_A00₀h
Address register (A0)
0000_A00₁h
Address register (A1)
0000_S0_B0h
Static base register (SB)
0000_F0_B0h
Frame base register (FB)
000000h
000000h
000000h
Contents of addresses
FFFFFEh to FFFFFCh
User stack pointer (USP)
Interrupt stack pointer (ISP)
Interrupt table register (INTB)
Program counter (PC)
DMAC-associated registers
b7
b0
00h
DMA mode register (DMD0)
b15
00h
XXXXh
DMA mode register (DMD1)
DMA transfer count register (DCT0)
XXXXh
DMA transfer count register (DCT1)
XXXXh
DMA transfer count reload register (DRC0)
b23
XXXXh
XXXXXXh
DMA transfer count reload register (DRC1)
DMA memory address register (DMA0)
XXXXXXh
DMA memory address register (DMA1)
XXXXXXh
DMA memory address reload register (DRA0)
XXXXXXh
DMA memory address reload register (DRA1)
XXXXXXh
DMA SFR address register (DSA0)
XXXXXXh
DMA SFR address register (DSA1)
Figure 5.3 CPU Register States after Reset
Rev.1.00 Jul 15, 2007 Page 36 of 352
REJ09B0385-0100