M32C8A Datasheet, PDF (115/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
11. Interrupts
11.4 High-Speed Interrupt
The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt routine in
three cycles. When the FSIT bit in the RLVL register is set to 1 (interrupt priority level 7 is used for the high-
speed interrupt), the interrupt that bits ILVL2 to ILVL0 in the Interrupt Control Register are set to 111b (level 7)
becomes the high-speed interrupt.
Only one interrupt can be set as the high-speed interrupt. To use the high-speed interrupt, do not set multiple
interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to 0 (interrupt priority level 7 is
used for interrupt) to use the high-speed interrupt.
Set the starting address of a high-speed interrupt routine in the VCT register.
When the high-speed interrupt is acknowledged, the FLG register value is saved into the SVF register and the
PC value is saved into the SVP register. A program is executed from an address indicated by the VCT register.
Use the FREIT instruction to return from a high-speed interrupt routine. Values saved into registers SVF and
SVP are restored to the FLG register and PC by executing the FREIT instruction.
The high-speed interrupt, and DMA2 and DMA3 share some of the registers. When using the high-speed
interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can still be used.
Figure 11.2 shows a procedure to use high-speed interrupt.
Start
I flag = 0
RLVL register: FSIT bit = 1
DMAII bit = 0
VCT regsiter: Set the starting address of
the high-speed interrupt routine
Set the peripheral function used for the high-speed
interrupt source
Interrupt Control Register:
Bits ILVL2 to ILVL0 = 111b (level 7)
I flag = 1
Operate peripheral functions
End
Interrupt disabled
Interrupt priority level 7 is used for the high-speed interrupt
Interrupt priority level 7 is used for interrupt
Set the interrupt priority level in the Interrupt Control Register
for the peripheral function used for the high-speed
interrupt source.
Interrupt enabled
Figure 11.2 Procedure to Use High-Speed Interrupt
Rev.1.00 Jul 15, 2007 Page 98 of 352
REJ09B0385-0100