M32C8A Datasheet, PDF (221/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
UARTi Baud Rate Register^{(1, 2)} (i = 0 to 4)
b7
b0
Symbol
Address
U0BRG to U2BRG
0369h, 02E9h, 0339h
U3BRG, U4BRG
0329h, 02F9h
Function
If the setting value is n,
the UiBRG register divides a count source by n+1
After Reset
Undefined
Undefined
Setting Range
RW
00h to FFh
WO
NOTES:
1. Read-modify-write instructions cannot be used to set the UiBRG register. Refer to Usage Notes for details.
2. Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register.
UARTi Transmit/Receive Control Register 1 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0C1 to U2C1
U3C1, U4C1
Address
036Dh, 02EDh, 033Dh
032Dh, 02FDh
After Reset
0000 0010b
0000 0010b
Bit Symbol
Bit Name
Function
RW
TE
Transmit enable bit
0: Transmit operation disabled
1: Transmit operation enabled
RW
TI
UiTB register empty flag
0: Data in the UiTB register
1: No data in the UiTB register
RO
RE
Receive enable bit
0: Receive operation disabled
1: Receive operation enabled
RW
RI
Receive complete flag
0: No Data in the UiRB register
1: Data in the UiRB register
RO
UilRS
UARTi transmit interrupt source 0: No data in the UiTB register (TI = 1)
select bit
1: Transmit operation is completed (TXEPT = 1)
RW
UiRRM
Continuous receive mode
enable bit
0: Continuous receive mode disabled
1: Continuous receive mode enabled⁽³⁾
RW
UiLCH
Data logic select bit⁽¹⁾
0: Not inverted
1: Inverted
RW
Special mode 3
0: Synchronization stopped
SCLKSTPB
Clock-divided synchronous
stop bit
1: Synchronization started
RW
UiERE
Special mode 4
0: Not output
Error signal output enable bit⁽²⁾ _{1: Output}
NOTES:
1. The UiLCH bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode), 100b
(UART mode, 7-bit data length), or 101b (UART mode, 8-bit data length). Set the UiLCH bit to 0 when bits SMD2 to SMD0 are
set to 010b (I²C mode) or 110b (UART mode, 9-bit data length).
2. Set bits SMD2 to SMD0 before setting the UiERE bit.
3. When the UiRRM bit is set to 1, set the CKDIR bit in the UiMR register to 1 (external clock) and also disable the RTS function.
Figure 17.8 U0BRG to U4BRG Registers, U0C1 to U4C1 Registers
Rev.1.00 Jul 15, 2007 Page 204 of 352
REJ09B0385-0100