M32C8A Datasheet, PDF (229/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
17. Serial Interfaces
17.1.1.1 CLK Polarity
As shown in figure 17.14, the CKPOL bit in the UiC0 register (i = 0 to 4) determines the polarity of the serial
clock.
(1) When the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the
falling edge and receive data input at the rising edge of the serial clock )
"H"
CLKi
"L"
"H"
TXDi
"L"
"H"
RXDi
"L"
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input
at the falling edge of the serial clock)
"H"
CLKi
"L"
"H"
TXDi
"L"
"H"
RXDi
"L"
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
The above applies under the following conditions:
- UFORM bit in the UiC0 register is set to 0 (LSB first)
- UiLCH bit in the UiC1 register is set to 0 (not inverted).
NOTES:
1. The CLKi pin output level is "H" when no transmit and receive operation is in progress.
2. The CLKi pin output level is "L" when no transmit and receive operation is in progress.
(note 1)
(note 2)
Figure 17.14 Serial Clock Polarity
Rev.1.00 Jul 15, 2007 Page 212 of 352
REJ09B0385-0100