M32C8A Datasheet, PDF (90/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
9. Clock Generation Circuits
Main Clock Division Register⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
MCD
Address
000Ch
After Reset
XXX0 1000b
Bit Symbol
Bit Name
Function
RW
MCD0
MCD1
MCD2
Main clock division
select bits⁽²⁾
MCD3
MCD4
−
(b7-b5)
Reserved bits
b4 b3 b2 b1 b0
RW
1 0 0 1 0: Divide-by-1 (no division) mode
0 0 0 1 0: Divide-by-2 mode
0 0 0 1 1: Divide-by-3 mode
RW
0 0 1 0 0: Divide-by-4 mode
0 0 1 1 0: Divide-by-6 mode
0 1 0 0 0: Divide-by-8 mode
RW
0 1 0 1 0: Divide-by-10 mode
0 1 1 0 0: Divide-by-12 mode
0 1 1 1 0: Divide-by-14 mode
RW
0 0 0 0 0: Divide-by-16 mode
Do not set to values other than the above
RW
Read as undefined value
−
NOTES:
1. Set the MCD register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. When stop mode or low-power consumption mode is entered, bits MCD4 to MCD0 become 01000b.
In on-chip oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit in the CM0 register is set to 1 (main
clock stops).
Figure 9.4 MCD Register
Rev.1.00 Jul 15, 2007 Page 73 of 352
REJ09B0385-0100