M32C8A Datasheet, PDF (113/372 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M32C/80 Series

M32C/8A Group
11. Interrupts
11.2 Software Interrupts
Software interrupts occur when particular instructions are executed. Software interrupts are non-maskable.
11.2.1 Undefined Instruction Interrupt
The undefined instruction interrupt occurs when the UND instruction is executed.
11.2.2 Overflow Interrupt
The overflow interrupt occurs when the INTO instruction is executed while the O flag in the FLG register is 1
(arithmetic operation overflow). Instructions that can set the O flag are: ABS, ADC, ADCF, ADD, ADDX,
CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX
11.2.3 BRK Interrupt
The BRK interrupt occurs when the BRK instruction is executed.
11.2.4 BRK2 Interrupt
The BRK2 interrupt occurs when the BRK2 instruction is executed.
Do not use this interrupt. This is for use with development support tool only.
11.2.5 INT Instruction Interrupt
The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can specify
software interrupt numbers 0 to 63. Software interrupt numbers 8 to 43 are assigned to the vector table used for
the peripheral function interrupt. This means that the MCU is able to execute the peripheral function interrupt
routine by executing the INT instruction. When the INT instruction is executed, values in the FLG register and
PC are saved to the stack. The relocatable vector of the specified software interrupt number is stored in PC.
The stack, where the data is saved, varies depending on a software interrupt number.
ISP is selected for software interrupt numbers 0 to 31. (The U flag in the FLG register becomes 0.) For
software interrupt numbers 32 to 63, SP which is selected immediately before executing the INT instruction is
used. (The U flag does not change.)
For the peripheral function interrupt, the FLG register value is saved and the U flag becomes 0 (ISP selected)
when an interrupt request is acknowledged. Therefore, for software interrupt numbers 32 to 43, SP to be used
can differ depending on whether an interrupt is generated by a peripheral function or by the INT instruction.
Rev.1.00 Jul 15, 2007 Page 96 of 352
REJ09B0385-0100